Mirroring from commit 106549a4362f6b499da522f8f8f5ed9f98388f87 from Coreboot upstream
This commit is contained in:
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// Main VGA bios initialization
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//
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// Copyright (C) 2009-2013 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2001-2008 the LGPL VGABios developers Team
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "biosvar.h" // SET_BDA
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#include "bregs.h" // struct bregs
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#include "hw/pci.h" // pci_config_readw
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#include "hw/pci_regs.h" // PCI_VENDOR_ID
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#include "hw/serialio.h" // serial_debug_preinit
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#include "output.h" // dprintf
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#include "std/optionrom.h" // struct pci_data
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#include "std/pmm.h" // struct pmmheader
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#include "string.h" // checksum_far
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#include "vgabios.h" // SET_VGA
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#include "vgahw.h" // vgahw_setup
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#include "vgautil.h" // swcursor_check_event
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// Type of emulator platform - for dprintf with certain compile options.
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int PlatformRunningOn VAR16;
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/****************************************************************
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* PCI Data
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****************************************************************/
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struct pci_data rom_pci_data VAR16 VISIBLE16 = {
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.signature = PCI_ROM_SIGNATURE,
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.vendor = CONFIG_VGA_VID,
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.device = CONFIG_VGA_DID,
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.dlen = 0x18,
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.class_hi = 0x300,
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.irevision = 1,
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.type = PCIROM_CODETYPE_X86,
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.indicator = 0x80,
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};
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/****************************************************************
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* PMM call and extra stack setup
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****************************************************************/
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u32
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allocate_pmm(u32 size, int highmem, int aligned)
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{
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u32 pmmscan;
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for (pmmscan=0; pmmscan < BUILD_BIOS_SIZE; pmmscan+=16) {
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struct pmmheader *pmm = (void*)pmmscan;
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if (GET_FARVAR(SEG_BIOS, pmm->signature) != PMM_SIGNATURE)
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continue;
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if (checksum_far(SEG_BIOS, pmm, GET_FARVAR(SEG_BIOS, pmm->length)))
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continue;
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struct segoff_s entry = GET_FARVAR(SEG_BIOS, pmm->entry);
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dprintf(1, "Attempting to allocate %u bytes %s via pmm call to %04x:%04x\n"
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, size, highmem ? "highmem" : "lowmem"
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, entry.seg, entry.offset);
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u16 res1, res2;
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u16 flags = 8 |
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( highmem ? 2 : 1 )|
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( aligned ? 4 : 0 );
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size >>= 4;
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asm volatile(
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"pushl %0\n"
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"pushw %2\n" // flags
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"pushl $0xffffffff\n" // Anonymous handle
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"pushl %1\n" // size
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"pushw $0x00\n" // PMM allocation request
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"lcallw *12(%%esp)\n"
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"addl $16, %%esp\n"
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"cli\n"
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"cld\n"
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: "+r" (entry.segoff), "+r" (size), "+r" (flags),
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"=a" (res1), "=d" (res2) : : "cc", "memory");
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u32 res = res1 | (res2 << 16);
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if (!res || res == PMM_FUNCTION_NOT_SUPPORTED)
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return 0;
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return res;
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}
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return 0;
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}
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u16 ExtraStackSeg VAR16 VISIBLE16;
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static void
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allocate_extra_stack(void)
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{
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if (!CONFIG_VGA_ALLOCATE_EXTRA_STACK)
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return;
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u32 res = allocate_pmm(CONFIG_VGA_EXTRA_STACK_SIZE, 0, 0);
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if (!res)
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return;
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dprintf(1, "VGA stack allocated at %x\n", res);
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SET_VGA(ExtraStackSeg, res >> 4);
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extern void entry_10_extrastack(void);
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SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10_extrastack));
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return;
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}
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/****************************************************************
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* Timer hook
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****************************************************************/
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struct segoff_s Timer_Hook_Resume VAR16 VISIBLE16;
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void VISIBLE16
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handle_timer_hook(void)
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{
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swcursor_check_event();
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}
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static void
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hook_timer_irq(void)
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{
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if (!CONFIG_VGA_EMULATE_TEXT)
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return;
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extern void entry_timer_hook(void);
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extern void entry_timer_hook_extrastack(void);
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struct segoff_s oldirq = GET_IVT(0x08);
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struct segoff_s newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook);
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if (CONFIG_VGA_ALLOCATE_EXTRA_STACK && GET_GLOBAL(ExtraStackSeg))
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newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook_extrastack);
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dprintf(1, "Hooking hardware timer irq (old=%x new=%x)\n"
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, oldirq.segoff, newirq.segoff);
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SET_VGA(Timer_Hook_Resume, oldirq);
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SET_IVT(0x08, newirq);
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}
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/****************************************************************
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* VGA post
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****************************************************************/
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static void
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init_bios_area(void)
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{
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// init detected hardware BIOS Area
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// set 80x25 color (not clear from RBIL but usual)
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set_equipment_flags(0x30, 0x20);
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// Set the basic modeset options
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SET_BDA(modeset_ctl, 0x51);
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SET_BDA(dcc_index, CONFIG_VGA_STDVGA_PORTS ? 0x08 : 0xff);
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// FIXME
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SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
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SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
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}
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int VgaBDF VAR16 = -1;
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int HaveRunInit VAR16;
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void VISIBLE16
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vga_post(struct bregs *regs)
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{
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serial_debug_preinit();
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dprintf(1, "Start SeaVGABIOS (version %s)\n", VERSION);
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dprintf(1, "VGABUILD: %s\n", BUILDINFO);
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debug_enter(regs, DEBUG_VGA_POST);
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if (CONFIG_VGA_PCI && !GET_GLOBAL(HaveRunInit)) {
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u16 bdf = regs->ax;
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if ((pci_config_readw(bdf, PCI_VENDOR_ID)
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== GET_GLOBAL(rom_pci_data.vendor))
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&& (pci_config_readw(bdf, PCI_DEVICE_ID)
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== GET_GLOBAL(rom_pci_data.device)))
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SET_VGA(VgaBDF, bdf);
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}
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int ret = vgahw_setup();
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if (ret) {
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dprintf(1, "Failed to initialize VGA hardware. Exiting.\n");
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return;
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}
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if (GET_GLOBAL(HaveRunInit))
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return;
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init_bios_area();
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if (CONFIG_VGA_STDVGA_PORTS)
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stdvga_build_video_param();
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extern void entry_10(void);
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SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10));
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allocate_extra_stack();
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hook_timer_irq();
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SET_VGA(HaveRunInit, 1);
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// Fixup checksum
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extern u8 _rom_header_size, _rom_header_checksum;
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SET_VGA(_rom_header_checksum, 0);
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u8 sum = -checksum_far(get_global_seg(), 0,
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GET_GLOBAL(_rom_header_size) * 512);
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SET_VGA(_rom_header_checksum, sum);
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}
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